In general, as the degree of integration in a semiconductor device increases, the sizes of the gate electrodes and the source/drain regions of a MOS transistor in the device decrease accordingly. This miniaturization of the structures of the MOS transistor requires a reduction in the length of a channel of the transistor. However, if the length of the channel in the MOS transistor is reduced below a certain size, undesirable electric characteristics (e.g., short channel effects) may occur.
To prevent these short channel effects from occurring in a MOS transistor, the horizontal length (i.e., the length of the gate electrode) should be decreased as well as the vertical length (i.e., the thickness of the gate insulating layer and the depth of the source/drain region). In addition, a decrease in the voltage of the driving power, an increase in the doping concentration of the substrate, and an efficient control for doping profiles in a channel area should be achieved.
Although the size of semiconductor devices has radically decreased, driving voltages applied to the semiconductor devices are still high. Thus, conventional NMOS transistors inevitably have several vulnerabilities. For example, a large potential gradient in a drain region may rapidly move electrons injected from a source region toward the drain region. Thus, hot carriers are readily generated around the drain region.
In order to enhance the structure of the conventional NMOS transistors generating the hot carriers, a lightly doped drain (hereinafter referred to as “LDD”) structure has been introduced.
A low concentration LDD region between a channel and a source/drain region is capable of mitigating the high drain-gate voltage around the drain junctions in the NMOS transistors. Thus, the otherwise large potential gradient in the drain region is decreased, thereby preventing the occurrence of hot carriers in the drain region. Various methods have been provided to fabricate a transistor having the LDD structure. One of the known methods for manufacturing a transistor having the LDD structure is to form spacers of insulating layers on the sidewalls of the gate electrodes.
Recently, as semiconductor devices have become increasingly integrated, a process for forming shallow junctions must be employed to efficiently prevent the short channel effect. The shallow junctions are formed by implanting B+ ions or BF2+ ions with a low implantation energy. However, as very large scale integration in the semiconductor devices is further progressed, the desired profiles of the junctions in the LDD structure are getting more difficult to achieve. Thus, a halo structure is additionally introduced to prevent the depletion areas of the source and drain regions from getting horizontally closer to each other. The halo structure does not affect the doping concentration in a channel area which determines the threshold voltage of the NMOS transistor.
The halo structure is formed by implanting halo ions (i.e., impurities of the opposite type to those of the source/drain region) around the junctions of the source/drain region adjacent to the gate electrodes in the NMOS transistor. Thus, the depletion areas of the source/drain region are reduced by forming diffusion areas which have higher impurity concentration than that of the wells adjacent to the junctions of the source/drain region.
FIG. 1 is a cross-sectional view illustrating a prior art NMOS transistor having a halo structure. Referring to FIG. 1, an active region is defined in a substrate 10 by isolation structures 11 in field regions. A gate insulating layer 13 is formed on the active region of the substrate 10. A gate electrode 20 is then formed on the gate insulating layer 13. Subsequently, N− type LDD regions 30 are formed around the gate electrode 20 in the active region. Halo regions (H) 40 are then formed under the N− type LDD regions 30 in the substrate 10. Subsequently, spacers of insulating layers 50 are formed on the sidewalls of the gate electrode 20. Finally, N+ type source/drain regions 60 are formed in the semiconductor substrate 10 on opposite sides of the gate electrode 20 and the spacers 50.
However, in such conventional NMOS transistors, after the ion implantations for forming the LDD regions 30 and the halo regions H are completed, a rapid thermal process (hereinafter referred to as “RTP”) is conducted to activate the impurities (e.g., As ions) in the LDD regions 30. When the impurities in the LDD regions 30 are activated by the RTP, diffusion of the impurities (e.g., boron) in the halo regions H toward the surface of the channel area is suppressed. Therefore, the threshold voltage of the NMOS transistor may be unstable, which detrimentally affects the electric characteristics of the NMOS transistor.
Kadosh et al., U.S. Pat. No. 6,589,847, describes a method of forming halo implant regions in a semiconductor device by performing a first angled implant process using a dopant material that is of a type opposite to a first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material.
Tran et al., U.S. Pat. No. 6,579,751, describes a method of forming integrated circuitry comprising first and second type MOS transistors.
Lee et al., U.S. Pat. No. 6,518,136, describes a method for making abrupt, PN junctions and haloes which use a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. Halo regions are implanted and activated by preferably using a spike annealing to prevent their diffusion.
Choi et al., U.S. Pat. No. 6,362,054, describes a method for forming a MOS transistor in a semiconductor substrate at a shallow implant angle by implanting a halo implant.
Rengarajan et al., U.S. Pat. No. 6,194,278, describes a method for forming a halo implant for semiconductor devices including the step of providing a substrate having a gate stack formed thereon.